ASUS New DDR3 T-Topology Design On Z77, H77 Motherboards

Not every innovation can be seen or interacted with; in fact, a lot of the work still goes into the very foundation of motherboard design. With motherboards, it’s never the case of taking off the shelf parts and putting your sticker on them. While you maybe just now buying and building your latest upgrade with a Z77 motherboard, ASUS engineers have been testing designs to improve performance and overclocking since this time last year. (Likewise, be safe in the knowledge that your next-next upgrade is being worked on right now!)

This is where ASUS’ new T-Topology for DDR3 falls in. It is a significant change to the fundamental DDR3 layout design, where instead of the daisy-chaining of banks in the channels, ASUS has created a T-style design that equals the trace length – and therefore data travel time – to DIMM 0 and DIMM 1.

To explain this further, keep in mind the principle formula: Time = Distance ÷ Speed

The speed of electron travel (equal to the speed of light) is always constant, and in making the distance traveled (the trace lengths) identical, this means the time traveled is now also the same. In theory this eliminates clock skew, but in reality there are outside influences such as DIMM quality, voltage consistency and memory controller (IMC) capacity under overclocked conditions, for example. Ultimately though, this topology upgrade means it is easier than ever to attain even more overclocking frequency and timing efficiency, and it further enhances the stability potential of 4-DIMM setups.

In its recent preview Anandtech has noticed what ASUS had implemented, and singled it out as a key design win between Intel Z77 based motherboards the team had viewed so far:

“ASUS have outsmarted Intel and have decided to take their technology to another level.  This is specifically in terms of memory, and how it is routed through the motherboard.  Typically, routing through the memory would occur in a daisy chain type environment, whereby if data was in the furthest memory slot away from the board, it would take longer to get to the CPU, and perhaps cause synchronization issues and delays – all reads had to be done serially between sticks in the same channel.

With ASUS’ new technology, they are essentially parallelizing memory reads that are commonly done serially between memory banks.  This is part of their ‘T-Topology’ memory subsystem, which allows synchronization to be dealt with in hardware.  This, according to ASUS, should allow for up to a 15% memory overclock beyond the previous methodology, where the motherboard is the limiting factor.  In this circumstance, we could be seeing some new memory records being set in dual channel memory.”

To give you a further idea of how painstaking this technology is to implement, below is just one of the PCB layer tracings we borrowed from a designers notes. Each data track has to be checked and lengthened or shortened accordingly, leading to some rather unique trace design ‘wiggles’ at the layer level: