Secondary Memory Timings

DRAM RAS to RAS Delay:

Also known as tRRD (activate to activate delay). Specifies the number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks.

DRAM Ref Cycle Time:

Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.

DRAM Write Recovery Time:

Defines the number of clock cycles that must elapse between a memory write operation and a Precharge command. Most DRAM configurations will operate with a setting of 9 clocks up to DDR3-2500. Change to 12~16 clocks if experiencing instability.

DRAM Read to Precharge Time:

Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (Precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased.

DRAM Four Activate Window:

Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum value for tFAW at the chipset level is 16 DRAM clocks.

As the effects of tFAW spacing are only realised after four activates to the same DIMM, the overall performance impact of tFAW is not large, however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value. As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks or tRRD * 4).

DRAM Write to Read Delay:

Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks.

As with tRTP this value may need to be increased according to memory density and memory frequency.

DRAM CKE Minimum Pulse width:

This setting can be left on Auto for all overclocking.

CKE defines the minimum number of clocks that must elapse before the system can transition from normal operating to low power state and vice versa.

DRAM RTL & IOL:

Unlike other timings, DRAM RTL and IOL are measured in memory controller clock cycles rather than DRAM bus cycles. These settings can safely be left on Auto for all normal use. The RTL and IOL define the number of memory controller cycles that elapse before data is returned to the memory controller after a read CAS command is issued. The IOL setting works in conjunction with RTL to fine tune DRAM buffer output latency. Both settings are auto-sensed by the memory controller during the POST process (memory training). Manual adjustment should not be necessary unless the system is being used in order to obtain maximum DRAM frequency screenshots (limited stability).