Tertiary Memory Timings

Most of these timings can be left on AUTO unless tweaking for SuperPi 32M. The best way to tune these settings if benchmarking is to set them to their maximum value and then decrease one step at time while monitoring stability at every change. We have color-coded text within this section to highlight more important timings over lesser ones.

Red = more important

Black = less important

On some settings , Intel have already enforced a 2 clock preset which the UEFI set value is added, and on others the memory controller calculates a minimum delay to which the UEFI value is added.

tRWDR (DD):

Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank or DIMM. A setting of 1 clocks works with some high performance DIMM configurations (dependent upon CAS). Relax to 2~7 clocks only if you are experiencing stability issues when running in excess of 4GB of memory over DDR3-2300.

tRWSR:

Sets the delay between a read command followed by a write command to the same rank. A setting of 2 is possible with high performance 2GB DIMMs. If experiencing instability or non-POST with CAS 8 or 9 then try a setting of 4+. To use a setting of 3 with CAS 9, set Stretch_ODT to 8 clocks using MemTweakit and monitor for performaqnce impact or change.

tRR (DD):

Sets the read to read delay where the subsequent read requires the access of a different DIMM. For high performance DIMMs start with a setting of 2 and increase to 3+ if you experience no POST.

tRR (DR):

Sets the delay between read commands when the subsequent read requires the access of a different rank on the same DIMM. This setting is an additive to an internally calculated value.

tRRSR:

Sets the delay between read commands to the same rank. From a performance perspective a setting of 4 clocks is optimal.

tWW(DD):

Sets the write to write delay where the subsequent write requires the access of a different DIMM. 4 clocks will work with most configurations; increase if using 4GB or 8GB DIMMs with all slots populated.

tWW(DR):

Sets the write to write delay where the subsequent write command requires the access of a different rank on the same DIMM; increase if using 4GB or 8GB DIMMs with all slots populated. tWWSR: Sets the delay between write commands to the same rank. From a performance perspective a setting of 4 clocks is optimal.

tWWSR:

Sets the delay between write commands to the same rank. From a performance perspective a setting of 4 clocks is optimal.