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Sets the voltage for the System Agent. It can be left on Auto for most overclocking.
May need adjustment on Sandybridge processors if using 16GB of memory or memory modules that contain ICs that represent a tough load to the memory controller. 1.05V is base, if adjusting increase in 0.025V steps and check stability at each increment. Maintaining a DC delta between this setting and DRAM voltage may be beneficial if using very high DRAM voltages (on Ivy Bridge, too).
CPU PLL Voltage:
For most overclocking, the minimum voltage requirements will be centered around 1.80V. If using higher processor multiplier ratios or DRAM frequencies over DDR3 2200, then a small over-voltage here can aid stability. Don note that the processor will become increasingly sensitive to PLL voltage changes at sub-zero temperatures and when nearing the maximum frequency the CPU is capable of.
Skew Driving Voltage:
Base is 1.05V. Adjustment is only required when running sub-zero processor temperatures or very high BCLKs. We have taken the time to enter offsets for you to work with within the LN2 profiles.
2nd VCCIO Voltage:
Is split from the VCCIO power rail to allow you to adjust both separately. As a starting point keep this close to VCCIO and then try setting this at a different value if chasing maximum processor overclocks (benhmarking use).
It can be left at default values for all overclocking. We have not observed any relationship between this voltage rail and any other in our testing to date.
Supplies power to the VTT input pin on DRAM memory modules. In most cases this setting can be left on Auto. At high DRAM clocks (in excess of DDR3-2400) increasing this voltage may help improve stability. Start with 0.85V and work up. Traditionally this setting should be at 50% of VDIMM, however in our testing we have found 0.85V a good starting point for improving stability in Super Pi 32M. A one or two step change above or below that can help 32M pass where it would otherwise fail.
DRAM DATA and CTRL References for all channels:
Allow adjustment of the DRAM read/write reference voltages for the DATA and CTRL signal lines. A setting of Auto defaults to 50% of VDIMM which should be adequate for almost all overclocking. Adjustment can sometimes be required when benchmarking memory at very high operating frequencies. In such instances a small reduction or increase (one step) above or below 50% can help aid stability in memory intensive benchmarks. Also if processors are sub-zero cooled, there may come a point where the memory controller becomes unstable regardless of operating frequency. This is where fiddling with these voltages can sometimes help pass benchmarks that would be otherwise unstable.
CPU Spread Spectrum:
Modulates processor core frequency in order to reduce the peak magnitude of radiated noise emissions. We recommend setting this to disabled if overclocking the as the modulation can interfere with system stability.
When enabled, this setting will return BCLK to a setting of 100 MHz (default) if the system fails to POST. Disabling it will NOT return BCLK to 100MHz when OC Failure is detected.
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