Before we start, please check out JJ's Z68 unboxing video to get an idea of component designation:
For our P67/Z68 series of motherboards, we’ve adopted easy (EZ) and Advanced UEFI BIOS interfaces to suit both plug-and-play and hands-on user mind-sets.
Upon entering UEFI BIOS, you will be greeted by this screen:
The “EZ” UEFI Menu
From here we can monitor primary system voltages, temperatures, monitor CPU fan speed, the time/date, one-touch overclock/power save or rearrange the boot priority of system drives by clicking and dragging the icons.
This menu is fairly self-explanatory; simply selecting one of these three options for your desired usage scenario will provide either a small power saving or a slight overclock after you save and exit BIOS.
If you’re looking at overclocking further or need to set specific parameters for on-board and plug-in components, then you’ll need to enter the Advanced Mode menu.
The Exit/Advanced Mode button in the top-right hand corner of the screen is used to either save/exit the BIOS or to access the Advanced Mode menu:
Our area of interest is the Ai Tweaker menu:
Ai Tweaker section –packed with overclocking related functions
Ai Overclock Tuner: Options are Auto, Manual and X.M.P.
Auto: This is the default setting, and needs to be changed to Manual if you wish to change BCLK (BCLK is the base reference frequency from which processor and other system bus frequencies are derived).
X.M.P: Extreme memory profile. Use this option if you have Sandy Bridge qualified XMP memory. X.M.P. profiles contain pre-sets for system buses and in some cases voltages. If the specified speed of the DIMMs is greater than the supported memory frequency of the platform, a platform specific X.M.P. profile option becomes mandatory because processor core and memory controller voltage requirements vary from architecture to architecture. High-speed enthusiast memory kits manufactured before the inception of the Sandybridge platform may not contain the necessary/adequate voltage offset settings for the system to be completely stable. In such instances, manual adjustments of memory controller voltage and memory timings may be necessary.
Selecting the X.M.P setting opens up options for X.M.P profile selection (the kit may contain more than one X.M.P profile), and also opens up the BCLK option for changing system bus frequency. Note that memory operating frequency and maximum CPU operating frequency are shown towards the top of the Ai Tweaker menu, while memory timings and voltage are displayed next to the XMP profile selection box.
BCLK/PCIe Frequency: This function becomes available if X.M.P or Ai Overclock Tuner “Manual” are selected. The base BCLK frequency is 100MHz. As the name implies, changing the BCLK frequency will also change PCIe frequency. The maximum CPU core frequency is derived via multiplication with the Turbo Ratio setting (final frequency is displayed at the top-left of the Ai Tweaker menu).
Bear in mind that the adjustment margin for this setting is not large - most processors have a range from 95~107 MHz.
Turbo Ratio: Options are “Auto”, “By All Cores” and “By Per Core”. A description of these settings is provided in the right-hand column of the UEFI BIOS and can be seen when the Turbo Ratio setting is selected.
By All Cores: This sets the CPU core frequency multiplier; multiplied by BCLK to give the target CPU frequency (under full load conditions if SpeedStep is active). “Auto”: Stock CPU multiplier Ratio used. Manual numerical entry of the desired Turbo Ratio is accepted.
Per Core: Allows setting the maximum Turbo multiplier of each physical processor core.
The available multiplier range is limited by both processor model and the ability of each CPU.
Internal PLL Overvoltage: Options are “Auto”, “Disabled” and “Enabled”. A manual setting of “Disabled” is recommended within the bounds of moderate overclocking. Using Core frequency multipliers in excess of 45X may need a setting of “Enabled”. The requirements of the “Enabled” setting will vary from processor to processor. The unfortunate side-effect is that resume from S3 sleep states is not possible when Internal PLL Overvoltage is set to “Enabled” - and only fixable by Intel who we are told are working on a solution.
Memory Frequency: “Auto” will automatically select a memory multiplier ratio according to memory module SPD (Serial Presence Detect). Manual selection of the available memory frequency multiplier ratios is possible and works according to the abilities of the DRAM and processor. Granular control of memory frequency is available by manipulating BCLK (within functional limits).
iGPU Max Frequency: Sets the maximum iGPU frequency in 50MHz steps (implied). Whether or not the processor core frequency ratio has any impact on the actual iGPU operating frequency is unknown by me at this time (TBD).
EPU Power Saving Mode: When “Enabled” is selected, utilizes power phase management based upon system loading to reduce system power consumption. A setting of “Disabled” is recommended for heavy overclocking.
OC Tuner: Our automated routine that overclocks a system based upon cooling and components. When selected the system will run a series of tests during system boot (do not be alarmed if your system reboots a few times after selecting this setting and saving and exiting BIOS – that’s normal). After the procedure is complete, you may wish to enter the operating system and run your preferred stability tests to confirm stable operation.
OC Tuner is handy for users who don’t wish to fiddle with BIOS settings manually, and make use of a reasonable overclock with minimal fuss. One contra-indication is that you may need to set “Internal PLL Overvoltage” to disabled if wishing to retain S3 functionality when the system is overclocked past a certain threshold.
DRAM Timing Control: Takes us to the DRAM timing sub-menu, where all primary, secondary and tertiary memory timings can be set:
These timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to experiment with various timings, the primary settings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, VCCIO and to a lesser extent CPU Core Voltage may be necessary to facilitate tighter timings.
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM or memory controller clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP. Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD - although the impact does increase if multiple page open and close requests are sent to the same memory IC, however, the likelihood of this is small due to interleaving and command scheduling. The Sandybridge memory controller is able to reschedule read and write commands very effectively in order to maximise open page hits, hence tRP tweaking is not as effective as it was on older platforms. This also goes some way towards explaining why Super PI 32M tweaks such as Waza are not as effective on this platform.
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued after a read command. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible. If however the banks in a rank have no open pages, and multiple banks need to be opened on that rank or across ranks, the impact of Command Rate increases.
Most DRAM module densities will operate fine with a 1N Command Rate. Memory modules containing older DRAM IC types may however need a 2N Command Rate.
DRAM RAS to RAS Delay: Also known as tRRD (activate to activate delay). Specifies the number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks (the chipset will revert to 4 clocks if a lower value is selected in BIOS).
DRAM Ref Cycle Time: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.
DRAM Refresh Interval: Also known as tREFI. Specifies the period that must elapse in DRAM clocks before a refresh command is issued. A larger value here is actually more aggressive as it increases the delay between refreshes. The charge stored in DRAM cells diminishes over time and must be refreshed to ensure that data is not lost. The minimum interval between refreshes varies according to DRAM ICs and the density of the modules – higher density modules generally need refreshing more often (lower value for tREFI). Refresh interval requirements also tend to vary according to DRAM temperature (changes in cell leakage rates) and VDIMM, so be prepared to experiment with values if sub-zero cooling is used on memory.
DRAM Write Recovery Time: Defines the number of clock cycles that must elapse between a memory write operation and a precharge command. Most DRAM configurations will operate with a setting of 10 clocks up to DDR3-1866. After that, relaxing to 12+ clocks may be necessary at DDR3-2000+.
DRAM Read to Precharge Time: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased.
DRAM Four Activate Window: Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum value for tFAW at the chipset level is 16 DRAM clocks.
The effects of tFAW spacing are only realised after four Activates to the same rank, so the overall performance impact of tFAW is not large (unless excessive spacing is used), however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value.
As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks or tRRD*4).
DRAM Write to Read Delay: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks. As with tRTP this value may need to be increased according to memory density and memory frequency.
DRAM CKE Minimum Pulse Width: Also known as tCKE. Specifies the minimum time the DRAM stays in self-refresh mode - during which the clock is held low for the duration of tCKE. Self-refresh mode is initiated during low power state system idle periods only (when the processor enters C3 and C6 states for example), so should not factor in overall system performance.
DRAM CAS Write Latency: Also known as CWL. Sets the column write latency timing for write operations to DRAM. For most purposes the minimum value should be equal to read CAS, as the timing constraints of accessing a column are the same. This timing is just as important as read CAS because data has to be written to DIMMs in order to be read.
DRAM RTL: Also known Round Trip Latency. RTL denotes the number of clock cycles it takes for a data to arrive at the memory controller after a read CAS command is issued. This value is specified in memory controller clock cycles (not DRAM clock cycles). On the Sandybridge architecture these values can safely be left on AUTO most of the time and do not need manual adjustment.
Most of these timings can be left on AUTO unless tweaking for SuperPi 32M
tWRDR (DD): Sets the delay period between a write command that is followed by a read command; where the read command requires the access of data from a different rank or DIMM. A value of 1 clock is possible on high performance memory. For higher density modules this value may need relaxing to 2~4 clocks as memory frequency is increased.
tRWDR (DD): Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank or DIMM. A setting of 3 clocks suits most DIMM configurations all the way to DDR3-2133. Relax only if you are experiencing stability issues when running in excess of 8GB of memory.
tRWSR: Sets the read to write delay timing where the write follows a read on the same rank. Can be left to 3 clocks for most configurations. 1~2 clocks may be possible at lower memory frequencies depending upon module density (sub DDR3-1866).
tRR(DD): Sets the read to read delay where the subsequent read requires the access of a different DIMM. 3 clocks will work with most configurations.
tRR(DR): Sets the read to read delay where the subsequent read requires the access of a different rank on the same DIMM. 3 clocks will work with most configurations at high memory frequencies. Only needs adjustment when double-sided DIMMs are used.
tRR(SR): Sets the read to read delay where the subsequent read accesses a different bank on the same rank. On the face of it the function of this timing seems akin to tRRD. We are not sure on its real usage scenario though suspect as both timings are included; this might be spacing where the page to be accessed is already open. The minimum internal spacing is 4 DRAM clocks; this hints at a possible open page scenario. A setting of 6 clocks can help overclocking 16GB configurations of memory to DDR3-2000+ speeds (memory controller/module capability permitting).
tWW(DD): Sets the write to write delay where the subsequent write requires the access of a different DIMM. 3 clocks will work with most configurations.
tWW(DR): Sets the write to write delay where the subsequent write command requires the access of a different rank on the same DIMM.
tWWSR: Sets the write to write delay where the subsequent write command requires the access of a different bank on the same rank.