CPU Clock Gen Filter: A setting of Auto is recommened for most overclocking. For memory speeds over DDR3-2200 use 10UF, for speeds over DDR3-2400 use 20UF. If using the 166 strap then a setting of Disabled is recommended.
Memory Frequency: “Auto” will automatically select a memory multiplier ratio according to memory module SPD (Serial Presence Detect). Manual selection of the available memory frequency multiplier ratios is possible and works according to the abilities of the DRAM and processor. Granular control of memory frequency is available by manipulating BCLK, while the base frequency of each divider is offset by changing the CPU strap settings (within functional limits).
EPU Power Saving Mode: When “Enabled” is selected, utilizes power phase management based upon system loading to reduce system power consumption. A setting of “Disabled” is recommended for heavy overclocking.
DRAM Timing Control: Takes us to the DRAM timing sub-menu, where all primary, secondary and tertiary memory timings can be set:
Load Elpida Hyper/ Tight PSC/Loose PSC RAW MHz Profile:
These profiles contain presets for the entire DRAM timing section and allow quick setup to facilitate overclocking or benchmarking. If you are using PSC or Elpida Hyper based modules, then try these profiles as a starting point. If overclocking with 64GB of memory, then using the RAW MHz Profile may be beneficial if you are experiencing any instability.
Rampage Tweak: A setting of Mode 2 is recommended for overclocking memory over DDR3-2000 or if using 64GB of memory.
Memory timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to make manual adjustments, the primary settings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, VCCSA and to a lesser extent CPU Core Voltage may be necessary to facilitate tighter timings.
Primary Timings
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP.Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD - although the impact does increase if multiple page open and close requests are sent to the same memory IC and to a lesser extent rank (there are 8 physical ICs per rank and only one page can be open per IC at a time, making up the total of 8 open pages per rank simultaneously).
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible. If however the banks in a rank have no open pages, and multiple banks need to be opened on that rank or across ranks, the impact of Command Rate increases.
Most DRAM module densities will operate fine with a 1N Command Rate. Memory modules containing older DRAM IC types may however need a 2N Command Rate.
Latency Boundary: Use a setting of Nearer for most modules. For older DRAM ICs a setting of Further may be beneficial.
Secondary TimingsDRAM RAS to RAS Delay:Also known as tRRD (activate to activate delay). Specifiesthe number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks.
DRAM Ref Cycle Time: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.
DRAM Write Recovery Time: Defines the number of clock cycles that must elapse between a memory write operation and a precharge command. Most DRAM configurations will operate with a setting of 9 clocks up to DDR3-2500. Change to 12~16 clocks if experiencing instability.
DRAM Read to Precharge Time: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased.
DRAM Four Activate Window: Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum value for tFAW at the chipset level is 16 DRAM clocks.
As the effects of tFAW spacing are only realised after four Activates to the same DIMM, the overall performance impact of tFAW is not large, however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value.
As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks or tRRD * 4).
DRAM Write to Read Delay: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks.
DRAM Write Latency: For the most part this setting can be left to Auto, and generally will default to Read CAS -1. So if CAS is set to 8 for example, Write CAS may default to 7. To facilitate stability at higher DDR3 speeds (over DDR3-2133) and if using 64GB of memory, then increasing Write CAS by 1~2 clocks should help at the expense of memory write speed performance.
Third Timings
Most of these timings can be left on AUTO unless tweaking for SuperPi 32M or if trying to maximize memory bandwidth. Most timings are internally limited to 4 clocks (DRAM burst length). Settings of 0-3 may be same as setting 4 in most cases.
tRRDR: Sets the read to read delay where the subsequent read requires the access of a different rank on the same DIMM. 4 clocks will work with most configurations at high memory frequencies. Only needs adjustment when double-sided DIMMs are used.
tRRDD: Sets the read to read delay where the subsequent read requires the access of a different DIMM. 4 clocks will work with most configurations.
tWWDR: Sets the write to write delay where the subsequent write command requires the access of a different rank on the same DIMM.
tWWDD: Sets the write to write delay where the subsequent write requires the access of a different DIMM. 4 clocks will work with most configurations.
tRWDR: Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank. A setting of 4 clocks suits most DIMM configurations all the way to DDR3-2133. Relax to 5~7 clocks only if you are experiencing stability issues when running in excess of 8GB of memory over DDR3-2300.
tRWDD: Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank or DIMM. A setting of 4 clocks suits most DIMM configurations all the way to DDR3-2133. Relax to 5~7 clocks only if you are experiencing stability issues when running in excess of 8GB of memory over DDR3-2300.
tWRDR: Sets the delay period between a write command that is followed by a read command; where the read command requires the access of data from a different rank. A value of 1 is possible on high performance memory. For higher density modules this value may need relaxing to 5~7 clocks as memory frequency is increased.