Sep 03, 2013 Written by: MarshallR

Recommended Settings For Overclocking Maximus VI Motherboards

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Recommended Settings For Overclocking

The following may help to achieve better overclocking results on the Maximus VI series overclocking and gaming motherboards.

Hardware Configurations for the ease of Overclock

DRAM

  • Install the memory in the Red slots first before occupying the Black ones.
  • Install DRAM from the Red slots that are closer to the CPU first.

DIMM-slotsiGPU

  • The integrated graphics inside the CPU silicon consumes power as well as generating heat. Logically then, you'll get a better overclock without using the internal graphics, instead using a PCI-Express graphics card. To shut-down the internal graphics, have iGPU Multi-Monitor Support set to Disabled in the BIOS to stop providing power to the iGPU when overclocking the CPU.

CPU Cooling

  • Use a qualified CPU cooler or a high-end CPU cooler, as the LGA1150 processor throttles down when CPU temperature exceeds its safety limit to reduce CPU temperature. It's strongly recommended to use either a CPU cooler that blows air downwards or that you have sufficient directional case airflow to the VRM heatsinks, so they are actively cooled when heavily overclocking.
  • For Haswell processors, due to the fact they are highly sensitive to the change in operational temperature, the OC margin may vary by a large degree between a selection of cooling solutions. From experimental results, aggressive cooling below zero should yield superb OC margins at reasonable voltages, however this obviously requires exotic cooling methods with environmental insulation to prevent condensation. (The CPU core temperature can be observed with Core Temp, for example: http://www.alcpu.com/CoreTemp/)

Software configurations to benefit overclocking

UEFI BIOS

overclocking-1

The Maximus VI Extreme features five sets of Overclocking Presets that enable an immediate access to a solid starting point for various O.C. combinations. Refer to appendix for the available presets.

  • Ai Overclock Tuner can be set to Manual to unlock BCLK/PCIE OC related options, set to X.M.P. to load the X.M.P. Profile from the DRAM module. X.M.P. can be used as a starting point to later modify the remaining options.
  • CPU Strap can be set to a different strapping to allow higher BCLK Frequency O.C. Users can try and raise or lower the CPU Strap if the desired BCLK cannot be achieved with your current CPU Strap. In addition, the relationship between the BCLK / PCIE / DMI Controller and the CPU Strap is that:

PEG Frequency = DMI Controller Frequency = 100 x (BCLK / CPU Strap)

Note: Usable CPU Strap varies with respect to the quality of the CPU.

If by any chance the change of CPU Strap is desired, one can leave the Source Clock Tuner at Auto for optimal O.C. capability utilizing higher CPU strap, or custom values. The Source Clock Tuner option will not be made available to adjustment unless the CPU Strap has been set to a fixed value.

  • PLL Selection can be set to Self Biased Mode (SB-PLL) to open wider frequency band for wider range of BCLK O.C. margin away from the configured CPU Strap, with the tradeoff of worse PCIE 3.0 compatibility due to the introduction of higher signal jitter at the PCIE. User can also leave at Inductance/Capacitance Mode (SB-LC) to minimize the introduction of jitter at the PCIE end for better PCIE 3.0 compatibility.
  • Filter PLL can be set to High BCLK Mode to slow down the filtering process in order to achieve a higher BCLK O.C. result with the trade off of more jitter. Generally speaking High BCLK Mode is only required when targeting for BCLK above 170MHz. User can happily leave it at Low BCLK Mode to allow better compatibility if otherwise.
  • ASUS MultiCore Enhancement can be Enabled to allow automatic configuration of the behavior of the Intel power saving and Turbo Boost for better overall performance when attempting to tweak the system in anyway outside the Intel default values.
  • Internal PLL Overvoltage can be set to Enabled to allow more CPU Turbo Ratio overclocking margin. However, please do keep in mind that the S3/S4 resume functionality on some DRAM modules may fail when enabling this function.
  • CPU bus speed: DRAM speed ratio mode can be altered between 100:100 and 100:133 when Ivy bridge processor is used. This will be very useful when trying to match the desired DRAM frequency, considering the DRAM frequency varies with respect to the change of DMI/PEG Frequency under 1:1 ratio, i.e. 1% raise in DMI/PEG Frequency will also bring 1% increase in DRAM Frequency.
  • Xtreme Tweaking can be enabled to yield better performance under older benchmarks applications.
  • CPU Graphics Max. Ratio is recommended to be left at the lowest 25 when targeting the highest CPU Frequency OC while the performance of the CPU integrated graphics is not the concern. This can help to reduce the power consumption and heat generated by the integrated graphics, yields more room for CPU core frequency tuning.

  • EPU Power Saving Mode is recommended to be left at Disabled before attempting to conduct manual O.C. to prevent degrading O.C. margin due to activities such as down voltage conducted by the EPU.
  • Fully Manual Mode is a special mode exclusively offered by Asus. Once enabled, will allow all six key voltages that are sent to the CPU to be set to a fixed value without the application of load-line (i.e. no voltage drop) rather than an offset from the voltage curve previously defined by Intel. Ideal for overclockers who are more used to traditional method of doing overvoltage. Note that under this mode, the CPU will no longer be able to lower any of the six key CPU voltages when the system idles down even if the CPU Power Saving Schemes such as EIST and the various C-States are enabled. Please disable this option if the use of the CPU built-in power saving schemes is desired.

  • The three most vital voltages going into the CPU, namely the CPU Core Voltage, CPU Graphics Voltage, CPU Cache Voltage, can be set to: Manual Mode to bring up the CPU Core Voltage Override, the CPU Graphics Voltage Override, and the CPU Cache Voltage Override option. Operating under this mode forces the CPU internal VR to feed a fixed value through the CPU Vcore, CPU Graphics, as well as the CPU Cache rail, each controls different part of the CPU. The manual mode will kick into effect as soon as the respective Voltage Override options are set to anything outside the default Auto. Under this mode, the CPU will no longer be able to lower its CPU Vcore voltage when the system idles down even if the CPU Power Saving Schemes such as EIST or the various C-States are enabled.

  • Offset Mode to bring up the Offset Mode Sign, as well as the CPU Core Voltage Offset, the CPU Graphics Voltage Offset, and the CPU Cache Voltage Offset option. Operating under this mode intakes the Intel defined SVID, summed with the three key Voltage Offsets, then outputted to the CPU Vcore, CPU Graphics as well as the CPU Cache rail each controls different part of the CPU. Leave the Voltage at Auto to load the Asus recommended offset value defined by the Asus OC Expert Team, or set to anything from +-0.001V and above to define the desired offset level. Setting to +-0.001V essentially makes the configured power rail to operate under factory default configuration.

  • Adaptive Mode, once configured will bring up the Offset Mode Sign, as well as the Voltage Offset and the Additional Turbo Mode Voltage for the CPU Vcore, CPU Graphics as well as the CPU Cache rail. The Adaptive Mode can be considered an extension of the Offset Mode. When working under this mode, the offset mode will be applied all the way up to the CPU Ratio before the CPU Ratio has been raised over the default Turbo Ratio. The configured Additional Turbo Voltage applies on the top of the result of the offset mode once the Turbo Boost enters O.C. state. Again, when either the offset of the additional turbo voltage are left at AUTO, the BIOS will load in the Asus recommended offset value defined by the Asus OC Expert Team. Setting to +-0.001V essentially makes the configured power rail to operate under factory default configuration.

  • SVID Support controls whether or not the CPU’s FIVR (Fully Integrated Voltage Regulator) should communicate with the external voltage regulator (Extreme Engine DIGI+ III) for the delivery of the CPU Input Voltage. Configuration this option to Enabled essentially establishes this communication while setting it to Disable forbids such communication, which yields better O.C. margin as compared with having it enabled. Considering this is outside the Intel CPU integrated Voltage Regulator, disabling SVID Support will “Not” affect the Intel integrated power saving functionalities such as EIST and the various C-States.
  • Dividing the “CPU Input Voltage” into “Initial CPU Input Voltage” and “Eventual CPU Input Voltage” enables users to apply different level of CPU Input Voltage before and after the POST sequence. This enables the weaker processors to utilize a higher voltage during the POST sequence to power up, then utilize a relatively lower voltage later to prevent overheat or overstressing the processor.
  • CPU Spread Spectrum options can be Disabled for better OC capability as Spread Spectrum attempts to generate minor fluctuation of the BCLK to prevent the emission of electrostatic interference from the CPU is not to exceed the health and safety regulation, which may in some ways affect the O.C. margin when every little change in BCLK needs to be take into consideration.
  • BCLK Recovery option can be Enabled to allow the system to boot under BIOS fail-safe mode while retaining the BCLK Frequency untouched.
  • CPU Load-Line Calibration can to be set to the highest Level 8 to ensure the CPU Input Voltage, i.e. the power going into the integrated voltage regulator is not to drop below the configured level for optimal OC results. This option can be lowered to reduce the amount of power consumption of the system when is under load.
  • CPU Voltage Frequency can to be set to Manual to allow selection of a fixed operating frequency for the Extreme Engine DIGI+ III. The higher the switching frequency, the faster the transient response, which yields a more stable delivery of CPU Input Voltage. This may help to yield just a little more BCLK O.C. margin for the CPU used. The effect of high CPU Voltage Frequency may vary with respect to the CPU used. It is highly recommended to Enable VRM Spread Spectrum or Enable Active Frequency Mode when not intending to set the CPU Fixed Frequency to the highest level to allow less emission of electromagnetic interference or better power saving.
  • VCCIN MOS Volt Control can be configured to a higher level for better O.C. stability with the tradeoff of a higher operation temperature, while configured to Active VGD enables the VCCIN MOS Volt Control option to be dynamically adjusted based on the load that the CPU FIVR drains from the Extreme Engine DIGI+ III.
  • CPU Power Phase Control can be set to Extreme to keep the number of active power phases of the CPU VRM at max for the whole time instead of powering down phases when CPU idles. This may gain a little more margin for stability when trying to achieve maximum core frequency. Alternatively, user can adopt Standard for down phase with respect to the change of the Intel PSI signal, optimized for better power saving, or define the custom down phase frequency manually. The faster the switch, the closer it is to setting CPU Power Phase Control to Extreme, just with the down phase capability.
  • CPU Power Duty Control can be set to Extreme to force the Extreme Engine DIGI+ III to function with respect to its maximum possible current delivery instead of a balanced temperature for a better delivery of power to the CPU integrated voltage regulator. This can also help to gain just a little more margin when trying to push CPU frequency to its max.
  • CPU Current Capability can be set to 140% to increase the CPU VRM over-current trip threshold. This allows the CPU integrated voltage regulator to drain more current from the Extreme Engine DIGI+ III, allowing the processor to achieve higher operating frequencies and increased software loads at those frequencies.
  • CPU Power Thermal Control can be set to a higher value when experiencing CPU throttling problems due to overheating Extreme Engine DIGI+ III. We recommended leaving this setting at default for all normal O.C., to ensure that the safe operating margins of the onboard CPU voltage supply are not breached. If experiencing throttling, the best advice is to cool the onboard Extreme Engine DIGI+ III with a fan to reduce temperature rather than altering this setting.
  • CPU Input Boot Voltage is the initial voltage that the Extreme Engine DIGI+ III delivers to the Intel FIVR (Fully Integrated Voltage Regulator) during the initial power sequence before the BIOS takes over.  This voltage is applied even before the Initial CPU Input Voltage option found under Extreme Tweaker is applied.  Careful adjustments of this voltage level may help to achieve a better O.C. result.
  • CPU Current Capability can be set to 130% to increase the DRAM VRM over-current trip threshold. This allows the CPU integrated voltage regulator to drain more current from the Extreme Engine DIGI+ III, allowing the DRAM to achieve higher operating frequencies and increased software loads at those frequencies.
  • DRAM Voltage Frequency can to be set to Manual to allow manual selection of a fixed VRM operating frequency. The higher the frequency, the faster the response, which yields a relatively stable delivery of VDIMM for the final push to gain just a little more DRAM overclocking capability for the DRAM used. The effect of high DRAM Voltage Frequency may vary with respect to the DRAM used.

  • DRAM Power Phase Control can be set to Extreme to keep the active power phase of the DRAM PWM at max for the whole time instead of shutting down a phase when DRAM idles. A setting of Extreme may gain a little more margin for DRAM overclocking when trying to achieve maximum DRAM frequency and or when populating all memory slots.
  • Long Duration Packet Power Limit defines the throttle point of when the CPU should throttle down when the power consumption exceed the defined level. This is also known as the first level of protection to prevent the CPU from been damaged due to overclocking. The unit is watte. The Intel default value of this option is the TDP(Thermal Design Power) of that processor. When left at AUTO, the BIOS will load the Asus recommended value defined by the Asus OC Expert Team for the ease of O.C.
  • Package Power Time Window defines the length of time in seconds that is allowed for the CPU to operate at above TDP yet below the Long Duration Package Power Limit. The unit is in seconds, with the maximum length limited at no more than 127.
  • Short Duration Package Power Limit defines the absolute highest power consumption that the CPU can sustain for a very short period of time to compensate the possibility of a sudden drain of power when under extreme high load. This is also considered the second layer of protection to prevent the CPU from been damaged due to overclocking. The unit is also in wattle. The Intel default of this value is 1.25 times the product defined TDP (i.e. the Long Duration Package Power Limit). Though Intel spec only requires the power plan to be capable of sustaining no less than 10ms when reaching the configured Short Duration Package Power Limit, the Asus motherboards can sustain much longer than that for the ease of O.C.
  • CPU Integrated VR Current Limit defines the highest current drain that is allowed by the CPU Integrated Voltage Regulator when under extreme high load. Raising this value to the maximum value of 1023.875 virtually means the disable of the current limit barrier on the Intel internal Voltage Regulator, which prevents the CPU from throttling down due to extensive current that is drained by the CPU when O.C.
  • Frequency Tuning Mode defines how quick the CPU integrated Voltage Regulator should operate. Rising to a higher value such as +6% enables smoother power delivery to the six key CPU voltages, while reducing this may help to reduce the overall power consumption of the CPU to some degrees.
  • Thermal Feedback defines whether or not the CPU should throttle down in respond to the overheat protection alarm triggered by the Extreme Engine DIGI+ III. This is the first layer of overheat protection of the Extreme Engine DIGI+ III and can be Disabled to allow more current drain from the Extreme Engine DIGI+ III till it reaches the absolute threshold temperature. It is highly recommended to keep the VRM heatsink fitted when disabling this option.
  • CPU Integrated VR Fault Management is recommended to be Disabled when attempting any level of overvoltage. This can help to yield a better O.C. capability involving the adjustment of any power options.
  • CPU Integrated VR Efficiency Management is recommended to be parked at High Performance to improve O.C. capability, whereas it can be left at Balanced to allow better power efficiency when the system is to be left at its default settings.

  • Power Decay Mode is the idle time power saving function of the CPU integrated voltage regulator. Can be set to Disabled to allow more O.C. margin while Enabled for better power efficiency, i.e. more power saving.
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  • Idle Power-in Response controls how fast the integrated voltage regulator should respond to the reduction of power level requests when the CPU idles down. This option can be set to Regular for better O.C. margin just in case if the CPU load fluctuates too fast. Setting to Fast allows the CPU to drain relatively less power from the integrated voltage regulator over time, making it more power saving when in action.
  • Idle Power-out Response controls how fast the integrated voltage regulator should respond to the rise of power level request when load is applied to the CPU. Setting to Fast enables the CPU to receive the higher voltage with a relatively shorter delay, which essentially helps to improve the O.C. margin under extensive O.C.
  • Power Current Slope defines the steepness of the current slope for the integrated voltage regulator. Setting to a smaller value such as LEVEL-4 enables the CPU to be throttled at a later time while setting to a bigger value does the exact opposite.
  • Power Current Offset defines the offset from the current slope that is defined in Power Current Slope option. Setting to a smaller value such as -100% enables the CPU to be throttled at a later time while with the trade off of receiving incorrect TDP reading as the result.
  • Power Fast Ramp Response defines how much faster should the integrated voltage regular response to the immediate need of a higher voltage level requested by the CPU. The higher the input value, the faster it will act. Can configure this option to the maximum value of 1.5 for better O.C. margin.
  • Power Saving Level 1 Threshold defines the minimum level of current consumption where the CPU should throttle down to save power. Setting to 0 to disable this function, or a higher value to push the throttle effect earlier.
  • Power Saving Level 2 Threshold defines the minimum level of current consumption where the CPU should throttle down to save power. Setting to 0 to disable this function, or a higher value to push the throttle effect earlier.
  • Power Saving Level 3 Threshold defines the minimum level of current consumption where the CPU should throttle down to save power. Setting to 0 to disable this function, or a higher value to push the throttle effect earlier.

  • The VCCIN Shadow Voltage is the voltage level that the Extreme Engine DIGI+ III delivers to the Intel FIVR (Fully Integrated Voltage Regulator) in during the POST sequence.  This voltage level change happens between the Initial CPU Input Voltage and the Eventual CPU Input voltage. You can leave the VCCIN Shadow Voltage at Auto unless you want to get input voltage very high or very low throughout the boot process.
  • Termination Anti-Aliasing can be enabled to smooth out the change of the PLL Termination Voltage, which may sometimes help to yield a better O.C. result.
  • PLL Termination Voltage (Initial / Reset / Eventual)is a very useful rail residing in the PCH ICC Integrated Clock Controller. It is useful when pushing BCLK, or conducting extreme CPU O.C. with subzero cooling using substances such as LN2. The default value is 1.2V, recommended starting point for tweaking this voltage rail includes anything below 1.25V or above 1.6V. Avoid utilizing voltage level between 1.25V to the CPU Input Voltage to avoid touching the dead-zone that is not liked by the processor.
    • When pushing BCLK (in excess of 160+MHz), it is advised to configure the PLL Termination Reset Voltage and Eventual PLL Termination Voltage to the same or above the Eventual CPU Input Voltage. Therefore, for example if the Eventual CPU Input Voltage is to be configured to 1.90V, then the PLL Termination Reset Voltage and the Eventual PLL Termination Voltage should be configured to 1.90V or higher for optimal effect. The same relationship should be kept when overvoltage under the OS as well.  Therefore, please also remember to adjust the PLL Termination Voltage before changing the CPU Input Voltage to ensure optimal result.
    • When working with BCLK O.C. below 160MHz, sometimes it makes the overclocked CPU more stable when the PLL Termination Voltage has been reduced. Setting the PLL Termination Voltage to 1.10V or 1.00V may make the processor more stable under high clocks, or when subzero cooling is in used. To put in simple terms, keep this value under 1.25V, or keep it the same or above the CPU Input Voltage for optimal result.
  • X-Talk Cancellation Voltage may sometimes be raised to allow more stable O.C. when experiencing O.C. failures such as BSOD Error Code 0124.  However, the effect is the exact opposite when the Max. Vcore Voltage option has been enabled under LN2 mode.  Under such configuration, it may be wise to reduce this voltage rail to bring better stability.  The default value is 1.00V.
  • Cancellation Drive Strength manages the drive strength of the X-Talk Cancellation Voltage rail.
  • PCH ICC Voltageis the voltage rail of the Integrated Clock Controller.  With the default value of 1.200V, it has a different sweet spot that varies with the change of the DMI Frequency.
    • For High DMI Frequency (>=115MHz), try 1.2500V or lower.
    • For Low DMI Frequency (<=86MHz), try 1.7000V or higher.
  • ICC Ringback Cancellercan be used to control the noise level at the Integrated Clock Controller, where the effect varies with respect to its application:
    • Enable to allow better High DMI Frequency O.C.
    • Disable to allow better Low DMI Frequency O.C.
  • Clock Crossing VBoot: This is the initial boot voltage supplied at the very moment when a positive clock that is fed to the processor intersects with the negative clock. Usually lower is better for better O.C. margin, where the default value is 1.15000v. Lowering this voltage rail may help to yield a better DMI Frequency O.C. with the trade off of compensating the PCIE 3.0 compatibility, hence it is advised to try and raise this voltage rail when PCIE 3.0 compatibility issues occurred due to insufficient Clock Crossing VBoot. From experience, 0.8000V can be a good compromised value under most cases. Depending on the BCLK configured, increasing to 1.65v or decreasing this value may help improve the Cold Boot Bug under LN2 extreme OC condition.
  • Clock Crossing Reset Voltage: This is the system reset voltage supplied at the very moment when a positive clock that is fed to the processor intersects with the negative clock. Usually lower is better for better O.C. margin, where the default value is 1.15000v. Lowering this voltage rail may help to yield a better DMI Frequency O.C. with the trade off of compensating the PCIE 3.0 compatibility, hence it is advised to try and raise this voltage rail when PCIE 3.0 compatibility issues occurred due to insufficient Clock Crossing Reset Voltage. From experience, 0.8000V can be a good compromised value under most cases.

  • Clock Crossing Voltage: This is the stable voltage supplied at the very moment when a positive clock that is fed to the processor intersects with the negative clock. Usually lower is better for better O.C. margin, where the default value is 1.15000v. Lowering this voltage rail may help to yield a better DMI Frequency O.C. with the trade off of compensating the PCIE 3.0 compatibility, hence it is advised to try and raise this voltage rail when PCIE 3.0 compatibility issues occurred due to insufficient Clock Crossing Voltage. From experience, 0.8000V can be a good compromised value under most cases.
  • PECI Voltage generally speaking does not do much, however, it is still recommended to syncronice the PCEI Voltage with the PCH Voltage for optimal effect.
  • BCLK Amplitude controls the amplitude of the BCLK fed into the processor. From a nominal 0.7v Amplitude at 0, it can go up to 1.40v with the amplitude at +5. The value of +5 works great for most O.C. applications.
  • DMI GEN2 can be disabled when targeting BCLK above 200MHz. (i.e. DMI Frequency >= 120MHz) can help to trade the CPU to PCH link performance with more room for high BCLK O.C.
  • DMI De-emphasis Control can be manually adjusted to obtain better DMI Frequency tuning margin, though the default -6dB is the optimal configuration for most applications.
  • SATA Drive Strength can be tuned to allow better SATA compatibility. The default is 0, and can be adjusted to both sides.
  • CPU PCIE Controller can be used to disable the CPU integrated PCIEx16 lane to allow better 2D benchmark performance.  Once this option is disabled, the PCIE_x4_1 slot will be the only functional slot available for user expansion.
  • GEN3 Preset can be adjusted to allow different management for the device installed onto the PCIE 3.0 slots.  Though AUTO works well for most applications, users can also try to switch between various presets to see if that yields better performance.  This is especially useful when conducting multiple graphics card benching utilizing SLI or CrossfireX.
  • PLX 0.9V Core Voltage / PLX 1.8V AUX Voltage can be used to control the supply voltage towards the PLX PEX8747 PCIE 3.0 bridge controller.
  • PCIE Clock Amplitude is very similar to the BCLK Amplitude, apart from it is for the PCIE Frequency rather than the BCLK Frequency.  User can try and see the effect of tweaking this option when pushing high PCIE Frequency due to the raise of BCLK Frequency.
  • Internal Graphicscan be utilized to disable the CPU Integrated Graphics to spare more room for CPU O.C.
    • Onboard devices may affect the overall OC margin in some rare case, it is advised to disable all unused onboard devices when attempting to achieve the highest possible CPUOC.
  • It is recommended to keep other options at their default position “Auto” for better OC capability utilizing the OC experience of the Asus OC specialist team.
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