Crosshair VII Hero Essential Info Thread

This post by The Stilt is useful to see what the SMU (FIT) determines as safe voltage for a Zen2 CPU under high loads.

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Thanks to the features recently added in HWInfo, it is rather easy to verify what kind of voltages are safe to your CPU specimen. As said before, each and every CPU is different in terms of silicon characteristics, even if they are the same SKU with consecutive serial numbers.

First, set PPT / TDC and EDC to sufficiently high values, which are unreachable in practice. Then, make sure that the CPU is running bone stock (outside the altered PBO limits). Practically meaning that there are no fixed frequencies, voltages, voltage offsets or load-line adjustments used.

Open HWInfo, go to the "Central Processor(s)" and make sure that "CPU PBO Scalar (Reliability Reduction)" reads 1.00x. Then run the worst-case multithreaded workload of your choice (the worst-case workload of your use). While the workload is running, check HWInfo sensors for the "CPU Core Voltage (SVI2 TFN)". That value is the practical one, which the silicon fitness monitoring has allowed and is safe, without loosing any reliability. You can double check that this value wasn't affected by any of the other limits (thermal, power, current): change PBO Scalar to 2x value and repeat the test. If the observed voltage has increased from doing that, then the figure is accurate for the workload you used.

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Originally Posted by bigtop1967

Exactly my thoughts - thanks for the extra data!

I have found while comparing my performance with others that I often beat those with 1900 FCLK anyway, indicating that some are pushing further than is beneficial..... Though of course we all want 1900 FCLK

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NP :) .

It could well be some are pushing too hard, but dunno. I can see some swings in say CB20, for example first run of the day when system is coolest I could see ~7450 points for multi and other times later I could see ~7200. In points it may seem a large swing, in % it's more akin to run to run variance.

Any how I think Zen2 has been a real nice experience to use, looking forward to Zen3 :) .

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Originally Posted by Riverdog64

I have the Crosshair Vii X-470 w/ Ryzen 7, Radeon 7. Used mostly for gaming, I was curious about the overclock presets in the bios. Most of you all are well beyond using such basic stuff, but for a newbie are they a safe way to start overclocking my system?

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Dunno never used them TBH.

Found this interesting video in a thread on deliding without heating CPU. Temperature reduction stated by poster doesn't match what I've seen in der8auer's videos on delid, but the poster has gone bare die, where as der8auer places IHS back with LM. Seems like two capacitors were knocked off CPU during the delid process, see this post.

Still not found time to update OP or create a Matisse Essentials, about here in thread starts Matisse.

*** edit ***

Peeps may have seen a Zen2 Timings Checker, it can be found in this post.

Attachment 83923

This post on OCN contains some fin area info of Bykski A-Ryzen-ThV2-X, EK Supremacy Evo in this post.

Now for some Ballistix action :) ...

Attachment 84006

R9 3900X (Batch Code: BF 1944SUT)
C7HWIFI UEFI 3004 AGESA Combo-AM4 1.0.0.4B
Crucial Ballistix Sport LT 2x16GB kit (BLS2K16G4D32AESB)

RX Vega 64
Intel 660P 1TB NVMe on M.2_1 of mobo
ASUS Hyper M.2 x16 Card with 2x Adata SX8200 Pro 1TB NVMe (PCI-E slot in bifurcation of 4x/4x)
2x SATA HDD 2TB

Bykski A-Ryzen-ThV2-X (AS5 TIM)
2x Magicool 360 G2 Slim rads (3x Arctic Cooling F12 PWM per rad, top as exhaust, front as intake)
EK XRES 140 Revo D5 PWM

Be Quiet Dark Base 900 with mesh mod to front, upper panel mesh airflow improved. 1x Be Quiet Silent Wings 3 140mm PWM 1000rpm used as rear exhaust.

No additional cooling to RAM, 3333MHz had done RAM Test of 200%, completed a bench of AIDA64 and when went to open Ryzen Master system froze. Upped VDIMM to 1.355V on rerun did not have same issue. Run upto 3600MHz was nice and easy, ~1hr into Kahru RAM Test saw 5 errors. 3666MHz even with some changes to slights changes to ProcODT/RTT/timings/voltages hasn't gained me further stability, all tests on that MEMCLK have so far had extremely high error count in <50% run of RAM Test. At times experienced BSOD.

All test data in this ZIP, organise by time to see process better of testing so far.

So far my opinion is it's decent RAM in context of price.

I saw on the Reddit thread people saying Micron E is easier on IMC, IMO hyperbole.

Samsung B die is more flexible, is more friendly IMO, same sorta testing I can be up at 3733MHz/3800MHz with ease. If you already have B die or it is costing not vastly more than Micron E it is the better buy still with Ryzen 3000 if you value ease of OC, etc, etc.

Will carry on with more testing :) .

I am now balled over with the price/performance of Micron E die :cool: ...

First this screenie, left to right:-

• 3x AIDA64 for usual timings I use on Samsung B die
• 3x AIDA64 for current timings I'm using on Micron E die.
• Initial testing for the Micron E die profile as used for 3x AIDA64.
• 3737% RAM Test for 3x AIDA64 3800C16, but VDIMM 1.365V.

Next 12.5K PASS in Kahru RAM Test for 3800C16 1.365V.

Here's an updated ZIP for 3800MHz testing so far, organise files by time, Setup means profile set in UEFI, WP means a Warm Post test run, SPx means count of testing on Same Post, when a filename is repeated exactly I'm just capturing data of the same test run but later in it.

An updated ZIP for Micron E die 3800MHz mixed testing of ~31hrs continuous uptime, organise files by time.

Filenames at beginning have:-

• Setup means test on POST when profile setup in UEFI.
• FCP means a full fold POST, ie power supply switched off from wall prior to POST.
• FP means a full POST from shutdown.
• WP means a warm POST test run.
• SPx means count of testing on same Post.
• When a filename is repeated exactly, just capturing data of the same test run but later.

An updated ZIP, organise files by time. On Micron E die 3800MHz Phase 1 mixed testing of ~48hrs continuous uptime, Phase 2 I have lowered VDIMM to set value of 1.36V, from past experience with board a read with DMM on Probeit point for this would be ~1.364V.

Wrapped up testing last night of 3800C16@1.36V at ~24hrs uptime, set 1.355V and had this result this morning, link

Since installing the kit on the 7th of Feb the rig has had no down time, am impressed by the kit TBH.

Are you on BIOS 3004 or 2901?
Thanks.

3800C16@1.35V with Micron E die 2x16GB 3200C16 bin

~9hrs Kahru RAM Test
~10hrs HCI v6.0
~4hrs Y-Cruncher

so far ~23.5hrs continuous uptime testing for that profile.

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Originally Posted by bluestang

Are you on BIOS 3004 or 2901?
Thanks.

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No problem, I'm using 3004.

Some timings I've used so far on the Micron E 2x16GB, link.

I managed to get SOC down to 1.025V as well, in this ZIP is most recent testing, 3x AIDA64 link.

Previously on 4x8GB (single sided/rank) when using 3800MHz, I had seen I could set tRTP 5, but it would still be 6 (left screenie). On 2x16GB (dual sided/rank) you can set below 10, but it does not take (right screenie).

Attachment 84122

*** edit ***

On OCN where I also posted this information a member pointed out that tRTP needs to be even when using gear dowm mode, link.

This prompted me to read a Micron DDR4 white paper and found at end of page 93/top page 94:-

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When operating in 2N gear-down mode, the following MR settings apply:

• CAS latency (MR0[6:4,2]): Even number of clocks
• Write recovery and read to precharge (MR0[11:9]): Even number of clocks
• Additive latency (MR1[4:3]): CL - 2
• CAS WRITE latency (MR2 A[5:3]): Even number of clocks
• CS to command/address latency mode (MR4[8:6]): Even number of clocks
• CA parity latency mode (MR5[2:0]): Even number of clocks

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So with GDME below must be even:-

• tCL
• tWR
• tCWL
• tRTP

Now I have tRTP of 8 with 3800MHz.

*** edit ***

A Samsung DDR4 PDF (page 82/83) also has same information as Micron.

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For the operation of geardown mode in 1/4 rate, the following MR settings should be applied.
CAS Latency (MR0 A[6:4,2]) : Even number of clocks
Write Recovery and Read to Precharge (MR0 A[11:9]) : Even number of clocks
Additive Latency (MR1 A[4:3]) : 0, CL -2
CAS Write Latency (MR2 A[5:3]) : Even number of clocks
CS to Command/Address Latency Mode (MR4 A[8:6]) : Even number of clocks
CA Parity Latency Mode (MR5 A[2:0]) : Even number of clocks

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*** edit 2 ***
Gear down mode is part of JEDEC DDR4 Rev B specification, so it's not a manufacturer specific implementation.