Impedance
The latest processor and DRAM architectures employ automated impedance training procedures to ensure a close match between driver and receiver impedance. The interconnect impedance specification (motherboard traces) between driver and receiver stages is provided by the platform chipset vendor. Depending upon the motherboard vendor and the motherboard model, the specification values supplied by the chipset vendor are sometimes used as a guideline only – rather than strictly adhered to. The motherboard vendor may find situations in which using a different line impedance or trace layout helps with overclocking margin and system performance. As platforms become more integrated, this is an area in which a motherboard vendor spends a significant amount of development time. At least, any good vendor
should spend time on these areas if they are charging more money for an overclocking centric end-product.
Again, the automated process of impedance matching is quite robust at stock and mild overclock frequencies. It’s when we get close to component and platform limits, that we start experiencing drift and increased sensitivity to parameter adjustments.
A closely matched driver, line, and receiver impedance is important. When closely matched, energy can be transferred from the driver to the receiver in an efficient and predictable manner. As with resistance, impedance is measured in Ohms – the difference being that impedance is used when dealing with AC signaling, as capacitance and inductance need to be taken into account.
If line impedance is not well matched, signal integrity will suffer – more overshoot, undershoot, and ringing effects manifest. By now, we should know that these things are bad for overclocking, as they eat into our all important timing budget:
Impedance mismatches give rise to signaling issuesDue to the laws of physics, impedance is affected by temperature; the voltage swing of a driver may change with temperature, as does line impedance of traces which are made of copper. To manage these changes, the system employs different types of POST test routines from cold power on and warm reset to tune/re-tune driver impedance.
The success of this training process is reliant on a number of factors:
The quality of interconnect: cheaper manufacturing processes, fewer PCB layers, and poor trace length matching, all eat into overclocking margin sooner rather than later. Even if we make things as good as we can from an engineering standpoint, the platform itself may have limitations regarding flexibility for custom layouts and trace impedance values. It is possible, at times, to make things “too good”, because the memory controller, or even the platform microcode does not have the requisite flexibility to cater for design enhancements.
During POST, the driver calibration routine will determine how many pull-up resistors are needed to match required impedance levels of the DRAM ICs (drive strength). As with motherboards and chipsets, DRAM vendors also follow target specs for driver impedance. The usual range is between 34~40 Ohms, although there may be provision to support a slightly wider range. Remember, we are dealing with finite resources; the system does not have an infinite number of drivers to match impedance for every scenario; the closest match has to be used. When a system is overclocked to its limit, disparity in temperatures at the time calibration is performed, and the temperature of the system when it is running applications in the operating system, can be sufficient for the system to crash or fail during calibration (failed POST). This can also happen if system voltages are not sufficiently tuned for the applied overclock – the system isn't at absolute limits, it just hasn't been tuned well enough to dial out instability by the user.
There’s also some insight here about why certain DRAM IC types fall out of favor from one platform to the next. If the DRAM IC vendor chose to build their part to an impedance value or at voltages that fall at the edge of design spec, it may not perform well on newer platforms, as the trend for Intel and AMD is always to reduce power consumption. These efficiency enhancements usually result in lower recommended/specified voltages. The drivers within the processor will be optimized for performance around that level. This does not mean to say the memory kit will not work with the platform; it simply may not reach the same frequency or same timing latencies as the platform it was built for.
Back on topic, as we increase memory operating frequency and data rates, the ability of the output stages to drive signal-levels sufficiently, starts to suffer – obviously, rail voltages can have a significant impact on this. Therein lie the reasons why we need to adjust voltages to facilitate overclocking or stability. Note we used the word “adjust”, and not “increase”. Increasing voltage works when there is sufficient overhead in drivers to meet the required slew rate, without suffering from overshoot and undershoot. In some cases, we may need to move the voltage to a different value rather than a higher value. This is more apparent when impedance matching is not “good”; in such cases we're likely to encounter stability issues when increasing or adjusting voltage levels.
This brings us back to using systematic and gradual overclocking methods: system voltages need to be tuned gradually. If voltage is increased to a high value without any form of evaluation, we may have pushed the system outside reliable signaling thresholds before we’ve truly evaluated what our parts can do (given more ideal operating parameters.)
We often get requests here for overclocking guides when a new platform is released. When asked why us/him/me? The reply is “you can tell me what the safe voltages are”, or “I don’t know how much voltage to use”. To be blunt, if this isn’t your first overclocking experience, taking such a stance is utter hogwash. You simply use a systematic and gradual approach and that in itself will guide you. It’s how we formulate the guides ourselves; we do things gradually and work out where the platform shows signs of issue with stability. Safe voltage levels for rails that are not related “directly” to signaling such as Vcore, can be evaluated easily by finding out how well frequency scales in return for each small step in voltage increase. At a point where a larger jump in voltage is required, fall back to the earlier point. Follow these simple guidelines and you’ll never be looking for someone to write a guide again.
That’s enough babble for now. It’s time to apply a real-world analogy to the effects of impedance...