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    ROG Enthusiast Array tt0ne PC Specs
    tt0ne PC Specs
    Laptop (Model)Eurocom Sky X7E2G
    MotherboardASUS ROG Maximus XI Apex
    ProcessorIntel Core i9-9900k
    Memory (part number)2x G.Skill TridentZ RGB F4-3866C18-16GTZR
    Graphics Card #1EVGA GeForce RTX 2080 Ti Kingpin
    MonitorAcer XB270HU
    Storage #1Samsung SSD 850 EVO 1TB
    Storage #2Samsung NVMe SSD 960 EVO 250GB
    CPU CoolerEKWB EK-Velocity RGB Full Nickel CPU Waterblock
    CasePhanteks Enthoo Elite ATX Super Tower (PH-ES916E_AG)
    Power SupplyeVGA SuperNOVA T2 (1600W) & eVGA BQ (850W)
    Keyboard Wooting One Analog
    Mouse SteelSeries Rival 700
    Headset Audeze Mobius 3D Head Tracking Headset
    Mouse Pad SteelSeries QCK Prism Cloth
    OS Windows 10 Professional
    Network RouterCustom Linux Box
    Accessory #1 X-rite ColorMunki
    tt0ne's Avatar
    Join Date
    Oct 2012
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    I finally got these sticks working with my Apex XI and figured I'd share my settings with anyone who may be searching and find this thread in the future. These settings are prime stable for me and are in my daily driver system so I push for maximum performance without compromising stability. It takes a lot of time to dial in these double sided 16 GB sticks hopefully this will save some time for others:

    NOTE: I had to use Maximus Tweak Mode 1. This causes the way IO Latency and RTL works with this specific memory. Normally with Mode 2 you'd dial in your latency settings by setting your IO Latency Offset to 21 and increase by one until the system no longer trained and then dial it back by one and set your IO Latency manually. With Mode 1 when set your offset to the same base of 21 but you decrease the number by 1 until you can no longer train. Additionally in this mode the offset changes RTLs and not the IOL. The IO Latency values will not change. With my sticks they stayed at 13 for the first DIMM and 14 for the second DIMM (well, since these are Double Sided DIMMs you really see 13/13/14/14). I was able to get both to 13 because once I was dialed you can almost always lower the second DIMM by one on the RTL and IOL manually. In other words, by using the IO offset at 21 and decreasing until I got to 16 I was left with 67/67/69/69/13/13/14/14 which I manually changed to 67/67/68/68/13/13/13/13. Also, to make it even more confusing I've noticed that how Mode 1 and Mode 2 interact with memory sticks and what they will affect and how they will effect stuff is not consistent but I don't think anyone outside of the Asus engineer's could explain why.

    Running a 9900k at 5.1 (synced AVX with no speed decrease) @ 1.27v and 4.6 ghz cache. Memory is running at 4000 Mhz at 1.45v.

    Applicable BIOS settings below (If it's not lsited then I left it at auto):

    [GROUP 1]

    Ai Overclock Tuner [Manual]
    BCLK Frequency [100.0000]
    ASUS MultiCore Enhancement [Enabled – Remove All limits]
    SVID Behavior [Auto]
    AVX Instruction Core Ratio Negative Offset [0]
    CPU Core Ratio [Sync All Cores]
    1-Core Ratio Limit [51]
    DRAM Odd Ratio Mode [Enabled]
    DRAM Frequency [DDR4-4000MHz]
    Xtreme Tweaking [Disabled]
    CPU SVID Support [Enabled]
    CPU Core/Cache Current Limit Max. [255.75]
    Min. CPU Cache Ratio [46]
    Max CPU Cache Ratio [46]
    BCLK Aware Adaptive Voltage [Enabled]
    CPU Core/Cache Voltage [Manual Mode]
    CPU Core Voltage Override [1.270]
    DRAM Voltage [1.4600]
    CPU VCCIO Voltage [1.23125]
    CPU System Agent Voltage [1.25625]
    PLL Termination Voltage [1.02000]
    CPU Standby Voltage [1.020]

    [GROUP 2]

    Maximus Tweak [Mode 1]
    DRAM CAS# Latency [18]
    DRAM RAS# to CAS# Delay [18]
    DRAM RAS# ACT Time [28]
    DRAM Command Rate [2N]
    DRAM RAS# to RAS# Delay L [6]
    DRAM RAS# to RAS# Delay S [4]
    DRAM REF Cycle Time [290]
    DRAM Refresh Interval [65535]
    DRAM WRITE Recovery Time [10]
    DRAM READ to PRE Time [6]
    DRAM FOUR ACT WIN Time [16]
    DRAM CKE Minimum Pulse Width [6]
    DRAM Write Latency [14]

    [GROUP 3]

    DRAM RTL (CHA DIMM0 Rank0) [67]
    DRAM RTL (CHA DIMM0 Rank1) [67]
    DRAM RTL (CHB DIMM0 Rank0) [68]
    DRAM RTL (CHB DIMM0 Rank1) [68]
    DRAM IOL (CHA DIMM0 Rank0) [13]
    DRAM IOL (CHA DIMM0 Rank1) [13]
    DRAM IOL (CHB DIMM0 Rank0) [13]
    DRAM IOL (CHB DIMM0 Rank1) [13]
    CHA IO_Latency_offset [18]
    CHB IO_Latency_offset [18]

    [GROUP 4]

    tRDRD_sg [6]
    tRDRD_dg [4]
    tRDWR_sg [14]
    tRDWR_dg [14]
    tWRWR_sg [6]
    tWRWR_dg [4]
    tWRRD_sg [28]
    tWRRD_dg [24]
    tRDRD_dr [6]
    tRDRD_dd [6]
    tRDWR_dr [14]
    tRDWR_dd [14]
    tWRWR_dr [8]
    tWRWR_dd [8]
    tWRRD_dr [6]
    tWRRD_dd [6]

    [GROUP 5]

    MRC Fast Boot [Disabled]
    MCH Full Check [Enabled]

    [GROUP 6]

    CPU Load-line Calibration [Level 6]
    Synch ACDC Loadline with VRM Loadline [Enabled]
    CPU Current Capability [140%]
    VRM Spread Spectrum [Disabled]
    Active Frequency Mode [Disabled]
    CPU Power Duty Control [Extreme]
    CPU Power Phase Control [Extreme]
    CPU Power Thermal Control [141]
    CPU VRM Thermal Control [Disabled]
    DRAM Current Capability [130%]
    DRAM Switching Frequency [Manual]
    Fixed DRAM Switching Frequency(KHz) [500]

    [GROUP 7]


    Intel(R) SpeedStep(tm) [Disabled]
    Turbo Mode [Enabled]
    Long Duration Package Power Limit [4095]
    Package Power Time Window [127]
    Short Duration Package Power Limit [4095]
    TVB Voltage Optimizations [Disabled]

    [GROUP 8]

    Realtime Memory Timing [Disabled]
    FCLK Frequency for Early Power On [1GHz]
    BCLK Spread Spectrum [Disabled]
    DMI Voltage [Auto]
    Core PLL Voltage [1.00000]

    [GROUP 9]

    Software Guard Extensions (SGX) [Disabled]
    Tcc Offset Time Window [Disabled]
    Intel (VMX) Virtualization Technology [Disabled]
    Boot performance mode [Turbo Performance]
    Intel(R) SpeedStep(tm) [Disabled]
    Intel(R) Speed Shift Technology [Disabled]
    Turbo Mode [Enabled]
    CPU C-states [Disabled]
    CFG Lock [Disabled]
    VT-d [Disabled]
    Above 4G Decoding [Enabled]
    Memory Remap [Enabled]
    Last edited by tt0ne; 04-12-2019 at 10:05 PM. Reason: 1st edit: explain RTL/IOL 2nd edit: made adjustments based on second long-term stability test



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