I agree that two iMCs seems likely. The iMCs can't be entirely symmetrical, imagine the complexity of implementing a "T-Topology" for uniform signal path lengths within the silicon itself, lol, especially given the constantly varying loads on each of the connected cores.
Not sure what effect AGESA would have. To be honest, I haven't adopted AMD yet and have only a vague understanding of how AGESA really works. Though compensating for AGESA-imposed variances of this sort could be corrected through firmware, yes?
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