Clock Skews


In most situations these won’t need to be changed, unless you are gunning for maximum reference clocks in order to exploit remaining margins on memory or CPU clock frequency.

An integrated clock generator IC located within the PCH (Southbridge) provides reference clock frequencies to all buses named in the BIOS.

Shamino has written up a few guidelines here to help give a few ideas of where to start.





Gross Simplification of Clock Skew

The actual function of the skew mechanism is to shift the start point of the rising edge of a clock signal across the time axis (in our case the offset scale is in picoseconds). The general notion with skew control is that components placed closer to the clock generator may need their clock signal delayed somewhat, while components placed further away may need their clock signal to be advanced. Although this is not always the case as trace capacitance, power supply noise and transient response can interfere with clock generation to some extent - resulting in the need for counter-adjustment in certain scenarios that don’t fit in with the previous statement.

Either way, the reason that adjustment may be required in the first place is that all of these components need to transfer data to one another; hence the rising edge of their respective data lines needs to be within a certain window to ensure reliable data transfer. At higher bus frequencies the alignment tolerance diminishes to such an extent that a manual shift of the reference clock feeding the offending bus may be necessary to ensure data transfer is still possible.

In the example below, the CPU is situated further away from the clock generator than the PCH. As a result of this the reference clock signal for the CPU arrives at the frequency synthesizer a little later than ideal.


Basic diagram for illustrative purposes only - clock distribution network not shown



The outcome of this is that as we increase the CPU frequency multiplier or change BCLK (the CPU reference clock frequency), our margin for reliable data transfer over all related clock domains deteriorates a little quicker than it would if the rising edge were situated closer to the ideal point. In this instance we advance the CPU clock skew by 300ps which shifts the start-up timing for the CPU clock drivers at the clockgen leading to a better time-aligned reference clock arrival at the CPU frequency synthesizer - resulting in an improved margin for overclocking:





Sampling margins increased due to better phase coherency between clock domains


Sure, there may be some write levelling routines built into the platform to de-skew timing mismatches between various data lines, thus the effects of skew adjustment on the Sandy Bridge platform are not large. However, benchmarking fanatics chasing maximum scores should spend a little time experimenting with these values to ensure stability and to extend overclocking headroom.